News

UPSET Presented at TAU 2025 Workshop

We are proud to share that our work, UPSET: SET Analysis and Optimization Flow for VLSI Circuits Based on Static Timing Analysis and Closed-loop In-place Optimizations, was presented by Prof. Christos Sotiriou at the TAU 2025 Workshop, held on May 1–2, 2025, in Seaside, California.

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The presentation took place during the session on Glitches, Soft Errors, and Asynchronous Circuits. It highlighted our ongoing research efforts within the TWINRELECT project, which is dedicated to advancing the reliability of electronic circuits and systems.

Participation in TAU 2025 reflects the recognition of our work by the broader design automation community. We were honored to contribute to the discussion on resilient electronics and share insights into how our methodologies support the development of reliable and robust VLSI systems for emerging technologies.

View the full workshop program: TAU 2025 Schedule